Analysts are extending Huawei's May 2026 LogicFolding announcement, which targets Ascend AI processors by 2030 and emphasizes 3D stacking to improve density without relying on traditional geometric shrinks, into a scenario of wafer-scale chips exceeding 30 kW. The projections tie LLM serving demands to extreme interconnect and memory requirements, then flag stacked SRAM plus a diamond microchannel layer as necessary for heat removal.
@teortaxesTex W2W HB is easier than D2D or D2W
ok what the hell. I missed this completely So, Huawei expects to deploy LogicFolding Ascends in 2030/31, and have >400 Mtr/mm^2, *and* have single-chip power draw of 30KW. I think this must mean heavy design for yield and, likely, Cerebras-style wafer-scale engines.
Existing Ascend 910 series parts draw 300-400 W each and rely on cluster-scale parallelism rather than single-chip extremes. Crossing into 30 kW territory would require packaging and cooling changes whose yield, cost, and reliability remain untested at that scale.
Huawei's public materials confirm the LogicFolding architecture and 2030 Ascend scaling intent but supply no figures for 30 kW draw or densities above 400 million transistors per square millimeter. Readers are left weighing how tightly those numbers follow from workload growth versus announced silicon details.
@zephyr_z9 Yes, but this is a very ambitious design on its own terms I guess it might not be that hard though. Something like SRAM on the bottom, diamond with microchannels on top, they could cool it.
@teortaxesTex W2W HB is easier than D2D or D2W
@zephyr_z9 @teortaxesTex need your thoughts on this paper @zephyr_z9 god. https://arxiv.org/abs/2606.04625
Analysts are extending Huawei's May 2026 LogicFolding announcement, which targets Ascend AI processors by 2030 and emphasizes 3D stacking to improve density without relying on traditional geometric shrinks, into a scenario of wafer-scale chips exceeding 30 kW. The projections tie LLM serving demands to extreme interconnect and memory requirements, then flag stacked SRAM plus a diamond microchannel layer as necessary for heat removal.
@teortaxesTex W2W HB is easier than D2D or D2W
ok what the hell. I missed this completely So, Huawei expects to deploy LogicFolding Ascends in 2030/31, and have >400 Mtr/mm^2, *and* have single-chip power draw of 30KW. I think this must mean heavy design for yield and, likely, Cerebras-style wafer-scale engines.